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4–10 Alpha Architecture Handbook
When a LDx_L instruction is executed without faulting, the processor records the target physi-
cal address in a per-processor locked_physical_address register and sets the per-processor
lock_flag.
If the per-processor lock_flag is (still) set when a STx_C instruction is executed (accessing
within the same 16-byte naturally aligned block as the LDx_L), the store occurs; otherwise, it
does not occur, as described for the STx_C instructions. The behavior of an STx_C instruction
is UNPREDICTABLE, as described in Section 4.2.5, when it does not access the same 16-byte
naturally aligned block as the LDx_L.
Processor A causes the clearing of a set lock_flag in processor B by doing any of the following
in B’s locked range of physical addresses: a successful store, a successful store_conditional, or
executing a WH64 instruction that modifies data on processor B. A processor’s locked range is
the aligned block of 2**N bytes that includes the locked_physical_address. The 2**N value is
implementation dependent. It is at least 16 (minimum lock range is an aligned 16-byte block)
and is at most the page size for that implementation (maximum lock range is one physical
page).
A processor’s lock_flag is also cleared if that processor encounters a CALL_PAL REI,
CALL_PAL rti, or CALL_PAL rfe instruction. It is UNPREDICTABLE whether or not a pro-
cessor’s lock_flag is cleared on any other CALL_PAL instruction. It is UNPREDICTABLE
whether a processor’s lock_flag is cleared by that processor executing a normal load or store
instruction. It is UNPREDICTABLE whether a processor’s lock_flag is cleared by that proces-
sor executing a taken branch (including BR, BSR, and Jumps); conditional branches that fall
through do not clear the lock_flag. It is UNPREDICTABLE whether a processor’s lock_flag is
cleared by that processor executing a WH64 or ECB instruction.
The sequence:
LDx_L
Modify
STx_C
BEQ xxx
when executed on a given processor, does an atomic read-modify-write of a datum in shared
memory if the branch falls through. If the branch is taken, the store did not modify memory
and the sequence may be repeated until it succeeds.
Notes:
• LDx_L instructions do not check for write access; hence a matching STx_C may take
an access-violation or fault-on-write exception.
Executing a LDx_L instruction on one processor does not affect any architecturally
visible state on another processor, and in particular cannot cause an STx_C on another
processor to fail.
LDx_L and STx_C instructions need not be paired. In particular, an LDx_L may be
followed by a conditional branch: on the fall-through path an STx_C is executed,
whereas on the taken path no matching STx_C is executed.