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B–8 Alpha Architecture Handbook
Table B–2: IEEE Floating-Point Trap Handling
Alpha Instructions
Hardware
1
PAL-
Code
OS
Completion
Handler
User
Signal
Handler
FBEQ FBNE FBLT FBLE FBGT
FBGE
Bits Only – No Exceptions
LDS LDT Bits Only—No Exceptions
STS STT Bits Only—No Exceptions
CPYS CPYSN Bits Only—No Exceptions
FCMOVx Bits Only—No Exceptions
ADDx SUBx INPUT Exceptions:
Denormal operand Trap Trap Supply sum
[Denormal Op
2
]
+/-Inf operand Trap Trap Supply sum –
QNaN operand Trap Trap Supply QNaN –
SNaN operand Trap Trap Supply QNaN [Invalid Op]
+Inf + –Inf Trap Trap Supply QNaN [Invalid Op]
ADDx SUBx OUTPUT Exceptions:
Exponent overflow Trap Trap Supply
+/–Inf
+/–MAX
[Overflow
3
]
Scale by bias
adjust
Exponent underflow and disabled Supply +0 – –
–
4
Exponent underflow and enabled Supply +0
and trap
Trap Supply
+/–MIN
denorm
+/–0
[Underflow
3
]
Scale by bias
adjust
Inexact and disabled – – – –
Inexact and enabled Supply sum
and trap
Trap – [Inexact]
MULx INPUT Exceptions:
Denormal operand Trap Trap Supply prod.
[Denormal Op
2
]
+/-Inf operand Trap Trap Supply prod. –
QNaN operand Trap Trap Supply QNaN –
SNaN operand Trap Trap Supply QNaN [Invalid Op]
0 * Inf Trap Trap Supply QNaN [Invalid Op]