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5–22 Alpha Architecture Handbook
5.6.3 Implied Barriers
There are no implied barriers in Alpha. If an implied barrier is needed for functionally correct
access to shared data, it must be written as an explicit instruction. (Software must explicitly
include any needed MB, WMB, or CALL_PAL IMB instructions.)
Alpha transitions such as the following have no built-in implied memory barriers:
• Entry to PALcode
• Sending and receiving interrupts
• Returning from exceptions, interrupts, or machine checks
• Swapping context
• Invalidating the Translation Buffer (TB)
Depending on implementation choices for maintaining cache coherency, some PALcode/cache
implementations may have an implied CALL_PAL IMB in the I-stream TB fill routine, but
this is transparent to the non-PALcode programmer.
5.6.4 Implications for Software
Software must explicitly include MB, WMB, or CALL_PAL IMB instructions according to the
following circumstances.
5.6.4.1 Single Processor Data Stream
No barriers are ever needed. A read to physical address x will always return the value written
by the immediately preceding write to x in the processor issue sequence.
5.6.4.2 Single Processor Instruction Stream
An I-fetch from virtual or physical address x does not necessarily return the value written by
the immediately preceding write to x in the issue sequence. To make the I-fetch reliably get the
newly written instruction, a CALL_PAL IMB is needed between the write and the I-fetch.
5.6.4.3 Multiprocessor Data Stream (Including Single Processor with DMA I/O)
Generally, the only way to reliably communicate shared data is to write the shared data on one
processor or DMA I/O device, execute an MB (or the logical equivalent
1
if it is a DMA I/O
device), then write a flag (equivalently, send an interrupt) signaling the other processor that the
shared data is ready. Each receiving processor must read the new flag (equivalently, receive the
interrupt), execute an MB, then read or update the shared data. In the special case in which data
1 In this context, the logical equivalent of an MB for a DMA device is whatever is necessary under the
applicable I/O subsystem architecture to ensure that preceding writes will be BEFORE (see Section
5.6.1.2) the subsequent write of a flag or transmission of an interrupt. Not all I/O devices behave
exactly as required by the Alpha architecture. To interoperate properly with those devices, some spe-
cial action might be required by the program executing on the CPU. For example, PCI bus devices
require that after the CPU has received an interrupt, the CPU must read a CSR location on the PCI
device, execute an MB, then read or update the shared data. From the perspective of the Alpha archi-
tecture, this CSR read can be regarded as a necessary assist to help the DMA I/O device complete its
logical equivalent of an MB.