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Index–7
Instruction stream. See I-stream
Instructions, overview
, 1–4
INSWH instruction
, 4–55
INSWL instruction
, 4–55
Integer division
, A–10
Integer registers
defined
, 3–1
R31 restrictions
, 3–1
INV bit
See also Arithmetic traps, invalid operation
Invalid operation enable (INVE)
FP_C quadword bit
, B–6
Invalid operation status (INVS)
FP_C quadword bit
, B–5
INVD bit. See Trap disable bits, invalid operation
IOV bit
See also Arithmetic traps, integer overflow
I-stream
coherency of
, 6–8
design considerations
, A–2
modifying physical
, 5–5
modifying virtual, 5–5
PALcode with
, 6–2
with caches
, 5–5
ITOFF instruction
, 4–124
ITOFS instruction
, 4–124
ITOFT instruction
, 4–124
J
JMP instruction, 4–22
JSR instruction
, 4–22
JSR_COROUTINE instruction
, 4–22
Jump instructions
, 4–18, 4–22
branch prediction logic
, 4–22
coroutine linkage
, 4–23
return from subroutine, 4–22
unconditional long jump
, 4–23
See also Control instructions
L
LDA instruction, 4–5
LDAH instruction
, 4–5
LDBU instruction
, 4–6
LDF instruction
, 4–91
LDG instruction
, 4–92
LDL instruction
, 4–6
LDL_L instruction
, 4–9
restrictions
, 4–10
with processor lock register/flag
, 4–10
with STx_C instruction
, 4–9
LDQ instruction
, 4–6
LDQ_L instruction
, 4–9
restrictions
, 4–10
with processor lock register/flag
, 4–10
with STx_C instruction
, 4–10
LDQ_U instruction
, 4–8
LDS instruction
, 4–93
with FPCR
, 4–84
LDT instruction
, 4–94
LDWU instruction
, 4–6
LEFT_SHIFT(x,y) operator
, 3–8
lg operator
, 3–8
Literals, operand notation
, 3–5
Litmus tests, shared data veracity
, 5–17
Load instructions
emulation of
, 4–3
FETCH instruction, 4–139
Load address
, 4–5
Load address high
, 4–5
load byte, 4–6
load longword
, 4–6
load quadword
, 4–6
load quadword locked, 4–10
load sign-extended longword locked
, 4–9
load unaligned quadword
, 4–8
load word, 4–6
multiprocessor environment
, 5–6
serialization
, 4–142
See also Floating-point load instructions
Load literal
, A–12
Load memory integer instructions
, 4–4
LOAD_LOCKED operator
, 3–8
Load-locked, defined
, 5–16
Location
, 5–11
Location access constraints
, 5–14
Lock flag, per-processor
defined
, 3–2
when cleared
, 4–10
with load locked instructions
, 4–10
Lock registers, per-processor
defined
, 3–2
with load locked instructions
, 4–10
Lock variables, with WMB instruction
, 4–148
Logical instructions. See Boolean instructions
Longword data type
, 2–2
alignment of
, 2–12
atomic access of, 5–2
LSB (least significant bit), defined for floating-point
,