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4–6 Alpha Architecture Handbook
4.2.2 Load Memory Data into Integer Register
Format:
Operation:
va ← {Rbv + SEXT(disp)}
CASE
big_endian_data: va’ ← va XOR 000
2
!LDQ
big_endian_data: va’ ← va XOR 100
2
!LDL
big_endian_data: va’ ← va XOR 110
2
!LDWU
big_endian_data: va’ ← va XOR 111
2
!LDBU
little_endian_data: va’ ← va
ENDCASE
Ra ← (va’)<63:0> !LDQ
Ra ← SEXT((va’)<31:0>) !LDL
Ra ← ZEXT((va’)<15:0>) !LDWU
Ra ← ZEXT((va’)<07:0>) !LDBU
Exceptions:
Instruction mnemonics:
Qualifiers:
Description:
The virtual address is computed by adding register Rb to the sign-extended 16-bit displace-
ment. For a big-endian access, the indicated bits are inverted, and any memory management
fault is reported for va (not va’).
LDx Ra.wq,disp.ab(Rb.ab)
!Memory format
Access Violation
Alignment
Fault on Read
Translation Not Valid
LDBU Load Zero-Extended Byte from Memory to Register
LDL Load Sign-Extended Longword from Memory to Register
LDQ Load Quadword from Memory to Register
LDWU Load Zero-Extended Word from Memory to Register
None