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4–78 Alpha Architecture Handbook
4.7.7.7 Underflow (UNF) Arithmetic Trap
An underflow occurs if the rounded result is smaller in magnitude than the smallest finite num-
ber of the destination format.
If an underflow occurs, a true zero (64 bits of zero) is always stored in the result register. In the
case of an IEEE operation that takes an underflow arithmetic trap, a true zero is stored even if
the result after rounding would have been –0 (underflow below the negative denormal range).
If an underflow occurs and underflow traps are enabled by the instruction, an underflow arith-
metic trap is signaled. However, under some conditions, the FPCR can dynamically disable the
trap, as described in Section 4.7.7.10, producing the result described in Section 4.7.10, as mod-
ified by the UNDZ bit described in Section 4.7.7.11.
4.7.7.8 Inexact Result (INE) Arithmetic Trap
An inexact result occurs if the infinitely precise result differs from the rounded result.
If an inexact result occurs, the normal rounded result is still stored in the result register. If an
inexact result occurs and inexact result traps are enabled by the instruction, an inexact result
arithmetic trap is signaled. However, under some conditions, the FPCR can dynamically dis-
able the trap; see Section 4.7.7.10 for information.
4.7.7.9 Integer Overflow (IOV) Arithmetic Trap
In conversions from floating to quadword integer, an integer overflow occurs if the rounded
result is outside the range –2**63..2**63–1. In conversions from quadword integer to long-
word integer, an integer overflow occurs if the result is outside the range –2**31..2**31–1.
If an integer overflow occurs in CVTxQ or CVTQL, the true result truncated to the low-order
64 or 32 bits respectively is stored in the result register.
If an integer overflow occurs and integer overflow traps are enabled by the instruction, an inte-
ger overflow arithmetic trap is signaled.
4.7.7.10 IEEE Floating-Point Trap Disable Bits
In the case of IEEE exception completion modes, any of the traps described in Sections 4.7.7.4
through 4.7.7.9 may be disabled by setting the appropriate trap disable bit in the FPCR. The
trap disable bits only affect the IEEE trap modes when the instruction is modified by any valid
qualifier combination that includes the /S (exception completion) qualifier. The trap disable
bits (DNOD, DZED, INED, INVD, OVFD, and UNFD) do not affect any of the VAX trap
modes.
If a trap disable bit is set and the corresponding trap condition occurs, the hardware implemen-
tation sets the result of the operation to the nontrapping result value as specified in the IEEE
standard and Section 4.7.10 and modified by the denormal control bits. If the implementation
is unable to calculate the required result, it ignores the trap disable bit and signals a trap as
usual.
Note that a hardware implementation may choose to support any subset of the trap disable bits,
including the empty subset.