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Chapter 4 Register Map and Descriptions
AT-MIO-16X User Manual 4-6
©
National Instruments Corporation
application of the appropriate load
signal.
12 SCANDIV Scan Divide—This bit controls the
configuration memory ssequencing
during scanned data acquisition. If
SCANDIV is set, then sequencing is
controlled by Counter 1 of the Am9513A
Counter/Timer. If SCANDIV is cleared,
the configuration memory is sequenced
after each conversion during scanning.
11 0 Reserved—This bit must always be set to
zero.
10 INTGATE Internal Gate—This bit controls internal
and external A/D conversations. When
INTGATE is set, no A/D conversions
take place. When INTGATE is cleared,
A/D conversions take place normally.
INTGATE can be used as a software
gating tool, or to inhibit random
conversions during setup operations.
9 RETRIG_DIS Retrigger Disable—This bit controls
retriggering of the AT-MIO-16X data
acquisition circuitry. When
RETRIG_DIS is set, retriggering of the
data acquisition circuitry is inhibited
until the end of the previous operation
is acknowledged by clearing the
DAQPROG bit in Status Register 0.
When RETRIG_DIS is cleared, the data
acquisition circuitry may be retriggered
any time following the end of the
previous acquisition sequence.
8 DAQEN Data Acquisition Enable—This bit
enables and disables a data acquisition
operation that is controlled by the
onboard sample-interval and sample
counters. If DAQEN is set, a software
DAQ Start or hardware (EXTTRIG*)
trigger starts the programmed counters,