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Chapter 4 Register Map and Descriptions
AT-MIO-16X User Manual 4-14
©
National Instruments Corporation
13 DIOPAEN Digital I/O Port A Enable—This bit
controls the 4-bit digital port A. If
DIOPAEN is set, the Digital Output
Register drives the DIO<4..1> digital
lines at the I/O connector. If DIOPAEN
is cleared, the Digital Output Register
drivers are set to a high-impedance state;
therefore, an external device can drive
the DIO<4..1> digital lines.
12 DMATCINT DMA Terminal Count Interrupt
Enable—This bit controls the generation
of an interrupt when a DMA terminal
count pulse is received from the DMA
controller in the PC AT. If DMATCINT
is set, an interrupt request is generated
when the DMA controller transfers the
final value on the primary DMA channel,
Channel A, or the secondary DMA
channel, Channel B. The interrupt
request is serviced by strobing the
appropriate DMATC Clear Register.
When DMATCINT is cleared, no DMA
terminal count interrupts are generated.
11 DACCMPLINT DAC Complete Interrupt Enable—This
bit controls the generation of an interrupt
when a DAC sequence completes. If
DACCMPLINT is set, an interrupt
request is generated when the sequence
completes. The interrupt request is
serviced by strobing the TMRREQ Clear
or DAC Clear Register. When
DACCMPLINT is cleared, completion of
a sequence does not generate an
interrupt. A DAC sequence ends by
running its course or when an error
condition occurs such as UNDERFLOW.
10 DAQCMPLINT DAQ Complete Interrupt Enable—This
bit controls the generation of an interrupt
when a data acquisition sequence
completes. If DAQCMPLINT is set, an
interrupt request is generated when the