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Chapter 5 Programming
AT-MIO-16X User Manual 5-28
©
National Instruments Corporation
Programmed Cycle Waveform Generation
A superset of the waveform functionality exists if DAC data buffer is
less than or equal to 2,048 for one channel, or less than or equal 1,024
per DAC for two channels. In these cases, the entire buffer resides
wholly within the DAC FIFO where the waveform circuitry cycles
through the buffer when the end is reached. This removes a large
burden on the PC bus for continually updating data in the DAC FIFO.
Also due to the smaller buffer size, the hardware has more control over
the updating and cycling through of the buffer. This enables the
waveform circuitry to perform cycle counting, programmed cycle
generation, and pulsed cyclic waveform generation.
To update the analog output DACs in programmed cycle waveform
generation mode, complete the sequence of programming steps in
Figure 5-8. The instructions in the blocks of the following flow chart
are enumerated in the Waveform Generation Programming Functions
section later in this chapter.