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National Instruments Corporation I-9 AT-MIO-16X User Manual
description, 4-49
DMA operations, 5-41
interrupt programming, 5-43
DAQ Start Register, 4-50
DAQCMPLINT bit, 4-14 to 4-15
DAQCOMP bit
description, 4-25
interrupt programming, 5-43
DAQEN bit
continuous channel scanning data
acquisition, 5-11
description, 4-6 to 4-7
interval-channel scanning data
acquisition, 5-14
DAQPROG bit, 4-25 to 4-26
data acquisition mode selection. See
Command Register 1.
data acquisition programming, 5-14 to 5-36
analog input circuitry, 5-5 to 5-6
analog output circuitry, 5-25
applying a trigger, 5-21
channel scanning, 5-10 to 5-11
continuous channel scanning,
5-10 to 5-11
interval-channel scanning,
5-12 to 5-14
clearing analog input circuitry, 5-14
cyclic waveform generation, 5-26 to 5-27
multiple-analog input channel
configurations, 5-15 to 5-16
programmed cycle waveform generation,
5-28 to 5-30
pulsed cyclic waveform generation,
5-30 to 5-32
resetting hardware, 5-22 to 5-24
sample counter(s), 5-17 to 5-20
sample-interval counter, 5-16 to 5-17
scan-interval counter, 5-20 to 5-21
servicing data acquisition
operations, 5-22
single conversions
flow chart, 5-6
generating single conversions, 5-6
reading single conversion result, 5-7
using SCONVERT or EXTCONV*
signal, 5-5 to 5-6
single-analog input channel
configurations, 5-15
single-channel data acquisition sequence,
5-7 to 5-9
waveform cycle counter, 5-34
waveform cycle interval counter,
5-34 to 5-36
waveform generation functions, 5-32
data acquisition rates
multiple-channel scanning rates,
A-5 to A-6
single-channel rates, A-4
data acquisition timing circuitry
block diagram, 3-5
definition, 3-8
multiple-channel data acquisition,
3-12 to 3-15
rates of data acquisition, 3-15
single-channel data acquisition,
3-9 to 3-12
single-read timing, 3-8 to 3-9
theory of operation, 3-8 to 3-12
data acquisition timing connections,
2-33 to 2-42
counter signal connections, 2-37 to 2-42
EXTCONVERT* signal, 2-34
EXTGATE* signal, 2-36
EXTSTROBE* signal, 2-33
EXTTMRTRIG* signal, 2-36
EXTTRIG* signal, 2-35
SCANCLK signal, 2-33
data buffers, PC I/O channel interface
circuitry, 3-3
DB_DIS bit, 4-23
DIFF (differential) input mode
definition (table), 2-8