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AT-MIO-16X User Manual I-12
©
National Instruments Corporation
F
fax and telephone support, D-2
Fax-on-Demand support, D-2
field wiring considerations, 2-42 to 2-43
FIFO. See ADC FIFO Register; DAC FIFO.
FIFO/DAC bit, 4-24
floating signal sources
description, 2-21
differential connections, 2-24 to 2-26
recommended configuration (table), 2-22
single-ended connections (RSE
configuration), 2-27
FOUT signal
Am9513A programmable frequency
output channel, 3-29
description (table), 2-19, B-6
RTSI switch connections, 3-30
timing signal source, 5-37
frequency measurements, 2-39
FTP support, D-1
functional overview. See theory of operation.
fuses and fusing
fusing of +5 V pin (table), 2-17, B-5
location of fuses (figure), 2-1, 2-2
power connections, 2-32
G
gain error
analog input circuitry, A-3
analog output circuitry, A-7
GATE, OUT, and SOURCE timing signals
counter signal connections, 2-37 to 2-42
RTSI bus interface circuitry, 3-30
timing I/O circuitry, 3-27 to 3-29
GATE1 signal
description (table), 2-18, B-5
RTSI switch connections (table), 5-38
GATE2 signal (table), 2-18, B-6
GATE2SEL bit
description, 4-24
pulsed cyclic waveform generation, 5-30
GATE5 signal (table), 2-18, B-6
General Event Strobe Register Group,
4-57 to 4-63
Calibration DAC 0 Load Register, 4-62
Calibration DAC 1 Load Register, 4-63
DMA Channel Clear Register, 4-58
DMATCA Clear Register
clearing analog output circuitry, 5-32
description, 4-59
interrupt programming, 5-43
programming DMA operations, 5-41
DMATCB Clear Register
clearing analog output circuitry, 5-32
description, 4-60
interrupt programming, 5-43
programming DMA operations, 5-41
External Strobe Register, 4-61
register map, 4-2
general-purpose timing signals. See counter
signal connections.
ground-referenced signal sources
description, 2-21
differential connections, 2-23
recommended configuration (table), 2-22
single-ended connections (NRSE
configuration), 2-28
H
hardware
installing, 2-13
resetting after data acquisition operation,
5-22 to 5-24