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Chapter 4 Register Map and Descriptions
©
National Instruments Corporation 4-15 AT-MIO-16X User Manual
data acquisition operation completes.
The interrupt request is serviced by
strobing the DAQ Clear Register. When
DAQCMPLINT is cleared, completion
of a data acquisition sequence does not
generate an interrupt. A data acquisition
sequence ends by running its course or
when an error condition occurs such as
OVERRUN or OVERFLOW.
9 I/O_INT Input/Output Interrupt Enable—This bit,
along with the appropriate mode bits,
enables and disables I/O interrupts
generated from the AT-MIO-16X. To
select a specific mode, refer to Table 4-3
for available modes and associated bit
patterns.
8 DMACHA DMA Channel A Enable—This bit
controls the generation of DMA requests
on DMA Channel A as selected in
Command Register 2. DMA requests are
generated from A/D conversions as well
as from timer updates. If DMACHA is
set, then requesting is enabled for DMA
Channel A. If DMACHA is cleared, no
DMA requests are generated on DMA
Channel A. To select a specific mode,
refer to Table 4-3 for available modes
and associated bit patterns.
7 DMACHB DMA Channel B Enable—This bit
controls the generation of DMA requests
on DMA Channel B as selected in
Command Register 2. DMA requests are
generated from A/D conversions as well
as from timer updates. If DMACHB is
set, requesting is enabled for DMA
Channel B. If DMACHB is cleared, no
DMA requests are generated on DMA
Channel B. To select a specific mode,
refer to Table 4-3 for available modes
and associated bit patterns.