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Chapter 4 Register Map and Descriptions
AT-MIO-16X User Manual 4-24
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National Instruments Corporation
If SRC3SEL is set, Source 3 is connected
to the DAC FIFO retransmit signal. In
the FIFO programmed cycle waveform
modes, this bit should be set so the
counter can access to the DAC FIFO
retransmit signal. If SRC3SEL is cleared,
Source 3 is connected to the SCANCLK
signal.
2 GATE2SEL Gate 2 Select—This bit is used to
configure the signal connected to Gate 2
of the Am9513 Counter/Timer. If
GATE2SEL is set, Gate 2 is connected to
Out 1 of the Am9513. This bit should be
set when using the FIFO pulsed
waveform generation mode. If
GATE2SEL is cleared, Gate 2 is
connected to the internal Gate 2 circuitry
on the AT-MIO-16X.
1 FIFO/DAC FIFO or DAC Write Select—This bit
controls the destination of writes to the
analog output DACs. DMA transfers to
the DACs are always buffered by the
DAC FIFO. Programmed I/O writes are
routed either to the DACs or through the
DAC FIFO by using the FIFO/DAC bit.
If FIFO/DAC is set, programmed I/O
writes to the DACs are buffered by the
DAC FIFO. If FIFO/DAC is cleared,
programmed I/O writes to the DACs
bypass the DAC FIFO and are
transmitted directly to the DACs.
0 EXTTRIG_DIS External Trigger Disable—This bit gates
the EXTTRIG* signal from the I/O
connector. If EXTTRIG_DIS is set,
triggers from EXTTRIG* are ignored by
the AT-MIO-16X circuitry. If this bit is
cleared, triggers from the EXTTRIG*
signal are able to initiate data acquisition
sequences.