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Chapter 3 Theory of Operation
AT-MIO-16X User Manual 3-6
©
National Instruments Corporation
Analog Input Circuitry
The analog input circuitry consists of an input multiplexer,
multiplexer-mode selection circuitry, a PGIA, calibration circuitry,
a 16-bit sampling ADC, and a 16-bit, 512-word deep FIFO.
A/D Converter
The ADC is a 16-bit, sampling, successive approximation ADC. With
16-bit resolution, the converter can resolve its input range into 65,536
different steps. This resolution generates a 16-bit digital word that
represents the value of the input voltage level with respect to the
converter input range. The ADC has two input modes that are software
selectable on the AT-MIO-16X board on a per channel basis: –10 to
+10 V, or 0 to +10 V. The ADC on the AT-MIO-16X is guaranteed to
convert at a rate of at least 100 ksamples/sec.
The data format circuitry is software programmable to generate either
straight binary numbers or two’s complement numbers. In unipolar
mode, values returned from the ADC are straight binary and result in
a range of 0 to 65,535. In bipolar mode, the ADC returns two’s
complement values, resulting in a range of –32,768 to +32,767.
Analog Input Multiplexers
The input multiplexer consists of a dual, eight-to-one CMOS analog
input multiplexer preceded by input protection resistors and has
16 analog input channels. Analog input overvoltage protection is ±25 V
powered on and ±15 V powered off. Input signals should be in the range
of +10 to –10 V for bipolar operation, and 0 to +10 V for unipolar
operation. Bipolar or unipolar mode configuration is programmed on a
per channel basis and is controlled through one of the registers in the
AT-MIO-16X register set.
Analog Input Configuration
Inputs can be configured for differential or single-ended signals on a per
channel basis through a register in the AT-MIO-16X register set. In
addition, single-ended inputs can be configured for referenced or
nonreferenced signals. In the differential configuration, one of input
Channels 0 through 7 is routed to the positive input of the PGIA, and
one of Channels 8 through 15 is routed to the negative input of the
PGIA. In the single-ended configuration, one of input Channels 0
through 15 is routed to the positive input of the PGIA. The negative