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Chapter 4 Register Map and Descriptions
AT-MIO-16X User Manual 4-26
©
National Instruments Corporation
data acquisition operation has
completed.
13 ADCFIFOHF* ADC FIFO Half-Full Flag—This bit
reflects the state of the ADC IFO. If
the appropriate conversion interrupts
are enabled, see Table 4-3, and
ADCFIFOHF* is clear, the current
interrupt indicates at least 256 A/D
conversions are available in the ADC
FIFO. To clear the interrupt, read the
ADC FIFO until it is empty,
ADCFIFOEF* is clear. If ADCFIFOHF*
is set, less than 256 ADC conversions are
available in the ADC FIFO.
12 ADCFIFOEF* ADC FIFO Empty Flag—This bit
reflects the state of the ADC FIFO. If
ADCFIFOEF* is set, one or more A/D
conversion results can be read from the
ADC FIFO. If the appropriate conversion
interrupts are enabled, see Table 4-3, and
ADCFIFOEF* is set, the current
interrupt indicates that A/D conversion
data is available in the ADC FIFO. To
clear the interrupt, the FIFO must be read
until it is empty. If ADCFIFOEF* is
cleared, the ADC FIFO is empty and no
conversion interrupt request is asserted.
11 DMATCA DMA Terminal Count Channel A—
DMATCA reflects the status of the DMA
process on the selected DMA Channel A.
When the DMA operation is completed,
DMATCA goes high and remains high
until cleared by strobing the DMATCA
Clear Register.
10 DMATCB DMA Terminal Count Channel B—
DMATCB reflects the status of the DMA
process on the selected DMA Channel B.
When the DMA operation is completed,
DMATCB goes high and remains high