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Chapter 4 Register Map and Descriptions
AT-MIO-16X User Manual 4-54
©
National Instruments Corporation
TMRREQ Clear Register
Accessing the TMRREQ Clear Register clears the TMRREQ and
DACCOMP bits after a TMRTRIG* pulse is detected. Clearing
TMRREQ when interrupt or DMA mode is enabled clears the respective
interrupt or DMA request.
Address: Base address + 1F (hex)
Type: Read-only
Word Size: 8-bit
Bit Map: Not applicable, no bits used
Strobe Effect: Clears the TMRREQ signal in Status Register 1 and its
associated interrupts, and clears the DAC COMP
signal in Status Register 1 and its associated interrupt
The analog output DACs can be updated internally and externally in the
waveform generation mode through the control of A4RCV. If A4RCV
is enabled, internal updating is selected and any signal from the RTSI
switch can control the updating interval. If OUT2 is to be used for
updating the DACs, A2DRV must also be enabled. If OUT5 is to be
used, A4DRV must be enabled as well. If A4RCV is disabled, external
updating is selected and the EXTTMRTRIG* signal from the I/O
connector is used for updating.
In all cases, a falling edge on the selected signal triggers the updating
mechanism in posted update mode. This trigger also sets the TMRREQ
bit in Status Register 1 and generates an interrupt or DMA request if so
enabled.