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Chapter 4 Register Map and Descriptions
©
National Instruments Corporation 4-23 AT-MIO-16X User Manual
Values can be directly written to the
DAC, but not through the DAC FIFO. If
DACGATE is cleared, updating of and
writing to the DACs proceeds normally.
6 DB_DIS Double Buffering Disable—This bit
controls the updating of the DACs. If
DB_DIS is set, writes to the DACs in
immediate and delayed update mode are
neither double-buffered nor deglitched.
If DB_DIS is cleared, the DACs are
double-buffered and deglitched.
5 CYCLICSTOP Cyclic Stop Enable—This bit controls
when a DAC sequence terminates. If this
bit is set when operating the DACs
through the FIFO in a cyclic mode, the
DAC circuitry will halt when the next
end of buffer is encountered. If this bit is
clear when the DACs are in a cyclic
mode, the DAC circuitry will restart
transmission of the buffer after reaching
the final point in the buffer. This bit is
functional only when the DAC circuitry
is in cyclic mode and data is stored
exclusively in the DAC FIFO.
4 ADCFIFOREQ ADC FIFO Request—This bit controls
the ADC FIFO Interrupt and DMA
Request mode. When ADCFIFOREQ is
set, ADC interrupt/DMA requests are
generated when the ADC FIFO is
half-full. In this case, the request is
removed only when the ADC FIFO has
been emptied of all its data. When
ADCFIFOREQ is cleared, ADC
interrupt/DMA requests are generated
when a single conversion is available in
the FIFO. In this case, the request is
removed when the ADC FIFO is empty.
3 SRC3SEL Source 3 Select—This bit is used to
configure the signal connected to
Source 3 of the Am9513 Counter/Timer.