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Chapter 3 Theory of Operation
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National Instruments Corporation 3-21 AT-MIO-16X User Manual
In Figure 3-11, the update trigger signal serves to update the previously
written value to the DAC. In the posted update mode, the DAC FIFO is
used to buffer the data. Requests are generated either when the FIFO is
not full or when the FIFO is less than half full. One of these two signals
generates the TMRREQ signal. In the example above, requesting is
generated when the FIFO is not full. Because each update removes a
value from the DAC FIFO, each update also results in the TMRREQ
signal being asserted. This sequence of events continues until the output
buffer data is exhausted.
There are effectively two different modes in which to operate the DAC
FIFOs in posted update mode. Data flows in and out at equal rates, or
data as initialized in the FIFO and once updating begins, the data is
cycled through when the end of the FIFO buffer is encountered. If
waveform cycles involving more than 2,048 values are required,
data must continuously flow into and out of the FIFO buffer to be
replenished. If waveform cycles of less than 2,048 points are required,
the data can be transferred to the DAC FIFO only once where it can be
cycled through to generate a continuous waveform. This mode removes
the burden on the PC to continuously transfer new data to the DAC
FIFO buffer, allowing it to perform other operations. In both cases,
waveforms like the one shown in Figure 3-12 can be realized.
Figure 3-12. Analog Output Waveform Circuitry
Whether the waveform size is greater than or less than 2,048 points, a
waveform can be generated that is seamless, that is, there will be no
gaps or missed points in the output waveform. If a point is missed for
any reason, the waveform circuitry will automatically stop updating
the DAC, and a waveform error signal will be generated that can be
monitored in Status Register 1. An error condition, or underflow, occurs
when data is extracted from the DAC FIFO faster than it enters, such
that at one point the DAC FIFO becomes empty.
Underflow errors occur because of software or hardware latencies in
acknowledging the signal requesting more data for the DAC FIFOs.
This condition can be prevented in the cyclic mode where the buffer
resides wholly in the DAC FIFO and is cycled through to generate a