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Chapter 4 Register Map and Descriptions
AT-MIO-16X User Manual 4-28
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National Instruments Corporation
I/O modes, TMRREQ must be cleared by
strobing the TMRREQ Clear Register.
6 DACCOMP DAC Sequence Complete—This bit
reflects the status of the DAC sequence
termination circuitry. When the DAC
sequence has normally completed, or
ended on an error condition, the
DACCOMP bit is set. If DACCOMP is
set prematurely, this indicates an error
condition. If interrupts are enabled, an
interrupt will be generated on this
condition. The interrupt is serviced by
strobing the TMRREQ Clear or DAC
Clear Register. While the sequence is in
progress, the DACCOMP bit is cleared.
5 DACFIFOFF* DAC FIFO Full Flag—This bit reflects
the state of the DAC FIFO. If
DACFIFOFF* is clear, the DAC FIFO is
full and is not ready to receive data. If
DACFIFOFF* is set, the DAC FIFO is
not full and is able to continue receiving
data. If the appropriate DAC and I/O
modes are enabled, interrupts or DMA
requests are generated until the DAC
FIFO is full.
4 DACFIFOHF* DAC FIFO Half Full Flag—This bit
reflects the state of the DAC FIFO. If
DACFIFOHF* is clear, the DAC FIFO
is at least half-full of data. If
DACFIFOHF* is set, the DAC FIFO is
not half-full of data. If the appropriate
DAC and I/O modes are enabled,
interrupts or DMA requests are generated
when the DAC FIFO is less than
half-full.
3 DACFIFOEF* DAC FIFO Empty Flag—This bit
reflects the state of the DAC FIFO. If
DACFIFOEF* is clear, the DAC FIFO is
empty. If DACFIFOEF* is clear before
the last point has been transferred to the