Filter
Top Products
AMD Geode™ LX Processors Data Book 121
CPU Core Register Descriptions
33234H
IF_TEST_DATA_MSR Register Map for Level-0 COF Cache Address
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
ADDR[31:0]
IF_TEST_DATA_MSR Bit Descriptions for Level-0 COF Cache Address
Bit Name Description
63:32 RSVD Reserved.
31:0 ADDR[31:0] Address Bits [31:0]. Linear address for which the entry contains data.
IF_TEST_DATA_MSR Register Map for Level-0 COF Cache Target
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
TARGET[31:0]
IF_TEST_DATA_MSR Bit Descriptions for Level-0 COF Cache Target
Bit Name Description
63:32 RSVD Reserved.
31:0 TARGET[31:0] Target Bits [31:0]. If an entry is valid and contains a predicted taken change of flow,
then this is the predicted target for the change of flow.
IF_TEST_DATA_MSR Register Map for Return Stack Addresses
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
ADDR[31:0]
IF_TEST_DATA_MSR Bit Descriptions for Return Stack Addresses
Bit Name Description
63:32 RSVD Reserved.
31:0 ADDR[31:0] Address Bits [31:0]. Linear address to which a Return instruction should return.