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AMD Geode™ LX Processors Data Book 571
GeodeLink™ PCI Bridge
33234H
6.15.6 Exception Handling
6.15.6.1 Out-Bound Write Exceptions
When performing an out-bound write on the PCI bus, two
errors may occur: target abort and PERR# assertion.
When a target abort occurs, the PCI Bus Interface block
must flush any stored write data. It must then report the
error. The assertion of PERR# is handled generically. The
failed transaction will not be retried.
6.15.6.2 Out-Bound Read Exceptions
When performing an out-bound read on the PCI bus, two
errors may occur: target abort and parity error. When a tar-
get abort occurs, the PCI Bus Interface block must return
the expected amount of data with sufficient error signals.
6.15.6.3 In-Bound Write Exceptions
When performing an in-bound write from the PCI bus, two
errors may occur: a detected parity error and a GLIU
exception. A GLIU exception cannot be relayed back to the
originating PCI bus master because in-bound PCI writes
are always posted. When a parity error is detected, the
PERR# signal must be asserted by the PCI Bus Interface
block. However, the corrupted write data will be passed
along to the GLIU.
6.15.6.4 In-Bound Read Exceptions
When performing an in-bound read from the GLIU, the
EXCEP flag may be set on any received bus-WORD of
data. This may be due to an address configuration error
caused by software or by an error reported by the source of
data. The asynchronous ERR and/or SMI bit will be set by
the PCI Bus Interface block and the read data, valid or not,
will be passed to the PCI Interface block along with the
associated exceptions. The PCI Bus Interface block should
simply pass the read response data along to the PCI bus.