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316 AMD Geode™ LX Processors Data Book
Display Controller Register Descriptions
33234H
11:8 DFHPSL Display-FIFO High Priority Start Level. This field specifies the depth of the display
FIFO (in multiples of 256 bytes) at which a high-priority request is sent to the memory
controller to fill up the FIFO. The value is dependent upon display mode. This field should
always be non-zero and should be less than the high-priority end level. Note that the set-
tings in the DC_ARB_CFG register (DC Memory Offset 00Ch) can also affect the priority
of requests.
7VGAE VGA Enable. When changing the state of this bit, both the DC and VGA should be
stopped, and not actively fetching and displaying data.
No other DC features operate with the VGA pass-through feature enabled, with the
exception of the CRC/signature feature, the filters, and the timing generator (when the fil-
ters or VGA fixed timings are enabled). All other features should be turned off to prevent
interference with VGA operation.
0: Normal DC operation.
1: Allow the hardware VGA use of the display FIFO and the memory request interface.
The VGA HSYNC, VSYNC, blank, and pixel outputs are routed through the back end
of the DC pixel and sync pipeline and then to the I/O pads.
6DECE Decompression Enable.
0: Disable display refresh decompression.
1: Enable display refresh decompression.
5CMPE Compression Enable.
0: Disable display refresh compression.
1: Enable display refresh compression.
4 FILT_SIG_SEL Filter Signature Select. When bit 23 is clear and this bit is set, the CRC mechanism at
the output of the scaler filter (before the flicker filter) is enabled. Setting this bit when bit
23 is also set has no effect. When both this bit and bit 23 are cleared, the CRC is taken at
the output of the DC, including the border/overscan pixels. Also note that the CRC calcu-
lation can be affected by the VBI CRC enable bit, located in DC_VBI_EVEN_CTL (DC
Memory Offset 0A0h[31].
3VIDE Video Enable.
0: Disable video port/overlay.
1: Enable video port/overlay.
2 CLR_CUR Color Cursor.
0: 2-bpp format.
1: 32-bpp color cursor.
1 CURE Cursor Enable.
0: Disable hardware cursor.
1: Enable hardware cursor.
0DFLE Display-FIFO Load Enable.
0: Disable display FIFO.
1: Enable display FIFO. Setting this bit high initiates display refresh requests to the mem-
ory controller at the trailing edge of vertical sync.
DC_GENERAL_CFG Bit Descriptions (Continued)
Bit Name Description