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AMD Geode™ LX Processors Data Book 645
Instruction Set
33234H
Instruction Notes for Instruction Set Summary
Notes a through c apply to real address mode only:
a. This is a protected mode instruction. Attempted execution in real mode results in exception 6 (invalid opcode).
b. Exception 13 fault (general protection) occurs in real mode if an operand reference is made that partially or fully
extends beyond the maximum CS, DS, ES, FS, or GS segment limit. Exception 12 fault (stack segment limit violation or
not present) occurs in real mode if an operand reference is made that partially or fully extends beyond the maximum SS
limit.
c. This instruction may be executed in real mode. In real mode, its purpose is primarily to initialize the CPU for protected
mode.
Notes e through g apply to real address mode and protected virtual address mode:
e. An exception may occur, depending on the value of the operand.
f. LOCK# is automatically asserted, regardless of the presence or absence of the LOCK prefix.
g. LOCK# is asserted during descriptor table accesses.
Notes h through r apply to protected virtual address mode only:
h. Exception 13 fault occurs if the memory operand in CS, DS, ES, FS, or GS cannot be used due to either a segment
limit violation or an access rights violation. If a stack limit is violated, an exception 12 occurs.
i. For segment load operations, the CPL, RPL, and DPL must agree with the privilege rules to avoid an exception 13
fault. The segment’s descriptor must indicate “present” or exception 11 (CS, DS, ES, FS, or GS not present). If the SS
register is loaded, and a stack segment not present is detected, an exception 12 occurs.
j. All segment descriptor accesses in the GDT or LDT made by this instruction automatically assert LOCK# to maintain
descriptor integrity in multiprocessor systems.
k. JMP, CALL, INT, RET, and IRET instructions referring to another code segment cause an exception 13, if an applicable
privilege rule is violated.
l. An exception 13 fault occurs if CPL is greater than 0 (0 is the most privileged level).
m. An exception 13 fault occurs if CPL is greater than IOPL.
n. The IF bit of the Flags register is not updated if CPL is greater than IOPL. The IOPL and VM fields of the Flags register
are updated only if CPL = 0.
o. The PE bit of the MSW (CR0) cannot be reset by this instruction. Use MOV into CR0 if you need to reset the PE bit.
p. Any violation of privilege rules as they apply to the selector operand do not cause a Protection exception; rather, the
zero flag is cleared.
q. If the processor’s memory operand violates a segment limit or segment access rights, an exception 13 fault occurs
before the ESC instruction is executed. An exception 12 fault occurs if the stack limit is violated by the operand’s
starting address.
r. The destination of a JMP, CALL, INT, RET, or IRET must be in the defined limit of a code segment or an exception 13
fault occurs.
Issue s applies to AMD-specific SMM and DMM instructions:
s. An invalid opcode exception 6 occurs unless the current privilege level is zero (most privileged) and either the instruc-
tion is enabled in SMM_CTL, the instruction is enabled in DMM_CTL, the processor is in system management mode,
or the processor is in debug management mode.
Issue t applies to the cache invalidation instruction with the cache operating in writeback mode:
t. The total clock count is the clock count shown plus the number of clocks required to write all “modified” cache lines to
external memory.
u. Non-standard processor core instructions. See Section 8.3.4 "Non-Standard Processor Core Instructions" on page 646
for details.