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AMD Geode™ LX Processors Data Book 487
Video Input Port Register Descriptions
33234H
6.10.1.5 GLD Power Management Register (GLD_MSR_PM)
6.10.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)
This register is reserved for internal use by AMD and should not be written to.
MSR Address 54002004h
Typ e R /W
Reset Value 000000000_ 00000005h
GLD_MSR_PM Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
RSVD 0 P1 0 P0
GLD_MSR_PM Bit Descriptions
Bit Name Description
63:4 RSVD Reserved.
3 RSVD Reserved. Always set to 0.
2P1 VIP Clock Power Mode.
0: Disable clock gating. VIP clock is always ON.
1: Enable active hardware clock gating.
The VIP input clock to the video input block is enabled when this bit is 0. When this bit is
1, the VIP input clock is enabled whenever the VIP reset bit (VIP Memory Offset 00h[0])
is 0 or if VIP_MODE (VIP Memory Offset 00h bit [3:1]) is in a non 000 state. This bit
defaults to 1.
1 RSVD Reserved. Always set to 0.
0P0 GLIU Clock Power Mode.
0: Disable clock gating. GLIU clock is always ON.
1: Enable active hardware clock gating.
GLIU clock is always on if the VIP reset bit (VIP Memory Offset 00h[0]) is 0. When the
VIP reset bit is 1 and this bit is 1, the internal VIP GLIU clocks are only turned on in
response to requests (memory mapped read/writes and MSR read/writes) from the GLIU.
This bit defaults to 1.
MSR Address 54002005h
Typ e R /W
Reset Value 000000000_ 00000000h