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AMD Geode™ LX Processors Data Book 353
Display Controller Register Descriptions
33234H
6.6.15 Even Field Vertical Timing Registers
6.6.15.1 DC Vertical and Total Timing for Even Fields (DC_V_ACTIVE_EVEN_TIMING)
This register contains vertical active and total timing information. These parameters pertain ONLY to even fields in inter-
laced display modes (The DC_V_ACTIVE_TIMING register (DC Memory Offset 050h) will take effect for odd fields in inter-
laced display modes.) Settings written to this register will not take effect until the start of the frame or interlaced field after
the timing register update bit is set (DC Memory Offset 008h[6] = 1).
DC Memory Offset 0E4h
Typ e R /W
Reset Value xxxxxxxxh
DC_V_ACTIVE_EVEN_TIMING Register Map
313029282726252423222120191817161514131211109876543210
RSVD V_TOTAL RSVD V_ACTIVE
DC_V_ACTIVE_EVEN_TIMING Bit Descriptions
Bit Name Description
31:27 RSVD Reserved. These bits should be programmed to zero.
26:16 V_TOTAL Vertical Total. This field represents the total number of lines for a given frame scan
minus 1. Note that the value is necessarily greater than the V_ACTIVE field (bits 10:0])
because it includes border lines and blanked lines.
15:11 RSVD Reserved. These bits should be programmed to zero.
10:0 V_ACTIVE Vertical Active. This field represents the total number of lines for the displayed portion of
a frame scan minus 1. Note that for flat panels, if this value is less than the panel active
vertical resolution (V_PANEL), the parameters V_BLANK_START, V_BLANK_END,
V_SYNC_START, and V_SYNC_END should be reduced by the following value
(V_ADJUST) to achieve vertical centering:
V_ADJUST = (V_PANEL - V_ACTIVE) / 2
If graphics scaling is enabled (and interleaved display is enabled), this value represents
the height of the final (scaled) field to be displayed. The height of the frame buffer image
may be different in this case; FB_ACTIVE (DC Memory Offset 5Ch) is used to program
the horizontal and vertical active values in the frame buffer when graphics scaling is
enabled.