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AMD Geode™ LX Processors Data Book 189
CPU Core Register Descriptions
33234H
5.5.2.98 L2 Cache Data MSR (L2_DATA_MSR)
L2_DATA_MSR is used to access the L2 cache data for diagnostic accesses.
5.5.2.99 L2 Cache Tag MSR (L2_TAG_MSR)
L2_TAG_MSR has the L2 cache tag, MRU and valid bits for diagnostic accesses.
MSR Address 00001923h
Typ e R /W
Reset Value 00000000_00000000h
L2_DATA_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
L2_DATA (High DWORD)
313029282726252423222120191817161514131211109876543210
L2_DATA (Low DWORD)
L2_DATA_MSR Bit Descriptions
Bit Name Description
63:0 L2_DATA L2 Cache Array Data. (Default = 0)
MSR Address 00001924h
Typ e R /W
Reset Value 00000000_00000000h
L2_TAG_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
L2_TAG RSVD
L2_MRU_2
L2_MRU_1
L2_MRU_0
RSVD
L2_VALID
L2_TAG_MSR Bit Descriptions
Bit Name Description
63:32 RSVD Reserved. (Default = 0)
31:15 L2_TAG L2 Cache Tag. Tag entry of the current way. (Default = 0)
14:7 RSVD Reserved. (Default = 0)
6 L2_MRU_2 L2 Cache 2 Most Recently Used. MRU bit for the current index. If equal to 1, ways 3-2
more recent than ways 1-0. (Default = 0)
5 L2_MRU_1 L2 Cache 1 Most Recently Used. MRU bit for the current index. If equal to 1, way 3
more recent than way 2. (Default = 0)
4 L2_MRU_0 L2 Cache 0 Most Recently Used. MRU bit for the current index. If equal to 1, way 1
more recent than way 0. (Default = 0)
3:1 RSVD Reserved. (Default = 0)
0 L2_VALID L2 Cache Valid. Valid bit for the current way.
0: Invalid. (Default)
1: Valid.