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310 AMD Geode™ LX Processors Data Book
Display Controller Register Descriptions
33234H
6.6.1.5 GLD Power Management MSR (GLD_MSR_PM)
6.6.1.6 GLIU0 Device Diagnostic MSR (GLD_MSR_DIAG)
This register is reserved for internal use by AMD and should not be written to.
MSR Address 80002004h
Typ e R /W
Reset Value 00000000_00000015h
GLD_MSR_PM Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
RSVD
VGA_GLCLK_PMODE
DCLK_PMODE
GLCLK_PMODE
GLD_MSR_PM Bit Descriptions
Bit Name Description
63:6 RSVD Reserved. Set to 0.
5:4 VGA_GLCLK_
PMODE
VGA GLIU0 Clock Power Management Mode. This field controls the internal clock
gating for the GLIU0 clock to the VGA module.
00: Clock is not gated.
01: Enable active hardware clock gating. Hardware automatically determines when it is
idle, and internally disables the GLIU0 clock whenever possible.
10: Reserved.
11: Reserved.
3:2 DCLK_PMODE Dot Clock Power Management Mode. This field controls the internal clock gating for
the Dot clock to all logic other than the VGA unit.
00: Clock is not gated.
01: Enable active hardware clock gating. Hardware automatically determines when it is
idle, and internally disables the Dot clock whenever possible.
10: Reserved.
11: Reserved.
1:0 G:CLK_PMODE GLIU0 Clock Power Management Mode. This field controls the internal clock gating
for the GLIU0 Clock to all logic other than the VGA unit.
00: Clock is not gated.
01: Enable active hardware clock gating. Hardware automatically determines when it is
idle, and internally disables the GLIU0 clock whenever possible.
10: Reserved.
11: Reserved.
MSR Address 80002005h
Typ e R /W
Reset Value 00000000_00000000h