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AMD Geode™ LX Processors Data Book 303
Display Controller Register Descriptions
33234H
Table 6-48. VGA Block Configuration Register Summary
DC
Memory
Offset Type Register Name Reset Value Reference
100h R/W VGA Configuration (VGA_CONFIG) 00000000h Page 355
104h RO VGA Status (VGA_STATUS) 00000000h Page 355
Table 6-49. VGA Block Standard Register Summary
I/O Read
Address
I/O Write
Address Register Name/Group Reset Value Reference
3CCh 3C2h (W) VGA Miscellaneous Output 02h Page 356
3C2h -- VGA Input Status Register 0 00h Page 357
3BAh or 3DAh
(Note 1)
-- VGA Input Status Register 1 01h Page 357
3CAh 3BAh or 3DAh
(Note 1)
VGA Feature Control xxh Page 357
3C4h VGA Sequencer Index 0xh Page 358
3C5h VGA Sequencer Data xxh Page 358
3B4h or 3D4h (Note 1) CRTC Index 00h Page 362
3B5h or 3D5h (Note 1) CRTC Data 00h Page 363
3CEh VGA Graphics Controller Index xxh Page 373
3CFh VGA Graphics Controller Data xxh Page 374
3C0h Attribute Controller Index/Data xxh Page 379
3C1h (R) 3C0h (W)
3C8h 3C7h (Palette
Read Mode)
Video DAC Palette Address 00h Page 382
3C8h (Palette
Write Mode)
3C7h-- Video DAC State 00h Page 383
3C9h Video DAC Palette Data 00h Page 383
3C6h Video DAC Palette Mask 00h Page 384
Note 1. The I/O addresses are determined by bit 0 of the Miscellaneous Output Register. See the description of this register
in Section 6.6.17.1 on page 356 for more information.