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AMD Geode™ LX Processors Data Book 183
CPU Core Register Descriptions
33234H
5.5.2.89 Bus Controller Configuration 0 MSR (BC_CONFIG0_MSR)
5 RETEN_TLB L2 TLB Retention Timer. Enable retention timer for L2 TLB BIST.
0: Disable.
1: Enable.
4 RUN_TLB L2 TLB Run. Start BIST test on L2 TLB arrays. Should read as 0 because BIST will have
completed before the MSR read can start.
3 RETEN_DATA Cache Data Retention Timer. Enable retention timer for cache data array BIST.
0: Disable.
1: Enable.
2 RUN_DATA Cache Data Run. Start BIST test on cache data array. Should read as 0 because BIST will
have completed before the MSR read can start.
1 RETEN_TAG Cache Tag Retention Timer. Enable retention timer for cache tag array BIST.
0: Disable.
1: Enable.
0 RUN_TAG Cache Tag Run. Start BIST test on cache tag arrays. Should read as 0 because BIST will
have completed before the MSR read can start.
MSR Address 00001900h
Typ e R /W
Reset Value 00000000_00000111h
DM_BIST_MSR Bit Descriptions
Bits Name Description
BC_CONFIG0_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
313029282726252423222120191817161514131211109876543210
RSVD PAUSEDLY RSVD
GPF_X
RSVD
CLK_ONS
SUSP
RSVD
RTSC_SUSP
RSVD
TSC_DMM
TSC_SUSP
TSC_SMM
RSVD
ISNINV
SNOOP
BC_CONFIG0_MSR Bit Descriptions
Bit Name Description
63:28 RSVD Reserved. Write as read.
27:24 PAUSEDLY Pause Delay. This field sets the number of clocks for which the bus controller will attempt
to suspend the CPU when a PAUSE instruction is executed. The approximate number of
clocks is PAUSEDLY*8. NOTE that the actual number of clocks that the CPU is sus-
pended will differ from this value, and will vary from pause to pause due to the overhead
of the suspend/unsuspend mechanism and any other CPU activity that would affect how
it responds to suspend requests.
Note also that bit 1 of MSR 00001210h must be set in order for suspend on pause to be
enabled.
23:21 RSVD Reserved.
20 GPF_X General Protection Faults on EXCEPT Flags. Generate general protection faults on
MSR accesses whose response packets have the EXCEPT flag set.
0: Disable.
1: Enable.