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318 AMD Geode™ LX Processors Data Book
Display Controller Register Descriptions
33234H
9:8 DISP_MODE Display Mode. Bits per pixel.
00: 8-bpp (also used in VGA emulation)
01: 16-bpp
10: 24-bpp (RGB 8:8:8)
11: 32-bpp
7 RSVD Reserved.
6TRUP Timing Register Update. Effective immediately.
0: Prevent update of working timing registers. This bit should be set low when a new tim-
ing set is being programmed, but the display is still running with the previously pro-
grammed timing set.
1: Update working timing registers on next active edge of vertical sync.
5 RSVD Reserved.
4VDEN Video Data Enable. Set this bit to 1 to allow transfer of video data to the VP.
3GDEN Graphics Data Enable. Set this bit to 1 to allow transfer of graphics data through the dis-
play pipeline.
2:1 RSVD Reserved.
0TGEN Timing Generator Enable. Effective immediately.
0: Disable timing generator.
1: Enable timing generator.
This bit must be set to 0 when using VGA mode unless the filters or VGA Fixed Timings
are also enabled (DC_GENERAL_CFG register, bit 18, DC Memory Offset 004h[18]).
DC_DISPLAY_CFG Bit Descriptions (Continued)
Bit Name Description