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296 AMD Geode™ LX Processors Data Book
Display Controller
33234H
6.5.7 Color Key Elimination
Additional logic, not shown in the diagrams, is used to pre-
serve the color key color. This logic, when enabled, adjusts
the alpha value for each filter input pixel in which a color
key match is detected. The filter then uses the alpha value
to determine if a pixel matches the color key. For informa-
tion on the interaction of cursor and color key, Table 6-35
on page 284.
The filter contains specialized logic to remove color key pix-
els from the blended output and replace them with nearby
pixels. This prevents halo effects if the color key contrasts
sharply with the surrounding graphics image.
For each of the 3-tap vertical filters, except the center one,
the replacement algorithm is as follows:
• If the top pixel is the only color key pixel, the center pixel
is used in its place.
• If the bottom pixel is the only color key pixel, the center
pixel is used in its place.
• If the center pixel is the only color key pixel, the top pixel
is used in its place.
• If any two pixels are color key pixels, the remaining pixel
is output to the horizontal filter.
• If all pixels are color key pixels, the bottom pixel is output
to the horizontal filter. (The vertical output is a color key
pixel and the alpha value is set accordingly.)
For the center 3-tap vertical filter, the algorithm is as fol-
lows:
• If the top pixel is a color key pixel, the center pixel is
used in its place.
• If the bottom pixel is a color key pixel, the center pixel is
used in its place.
• If the center pixel is a color key pixel, the center pixel is
output to the horizontal filter regardless of the values of
the other two pixels. (The vertical output is a color key
pixel, and the alpha value is set accordingly.)
The horizontal filter algorithm follows. Assume that the
pixel inputs are numbered 1-5, left to right.
• If pixel 1 is a color key pixel and pixel 2 is not, pixel 2 is
used in place of pixel 1.
• If pixel 1 and pixel 2 are both color key pixels, pixel 3 is
used in place of pixel 1.
• If pixel 2 is a color key pixel, pixel 3 is used in place of
pixel 2.
• If pixel 5 is a color key pixel and pixel 4 is not, pixel 4 is
used in place of pixel 5.
• If pixel 4 and pixel 5 are both color key pixels, pixel 3 is
used in place of pixel 5.
• If pixel 4 is a color key pixel, pixel 3 is used in place of
pixel 4.
• If pixel 3 is a color key pixel, pixel 3 is output from the
filter regardless of the values of pixels 1, 2, 4, and 5.
(The result is a color key pixel; the alpha value is set
accordingly.)
If the center pixel matches the color key, it is passed
through directly. If the center pixel does not match the color
key, then any other filter input pixel that matches the color
key is discarded and replaced by a nearby non-color-key-
matching neighbor.
6.5.8 Using the Graphics Filter
From a software perspective, the AMD Geode LX proces-
sor DC appears much like its predecessor in the
AMD Geode GX processor design. The graphics filter is
disabled by default, and the timing and addressing regis-
ters operate as before. One significant change is the addi-
tion of color key detection logic to the DC block. This logic
was previously only in the VP.
When enabling the VP for the purpose of scaling the output
image, some additional parameters must be programmed
(These parameters need not be programmed if the graph-
ics filter/scaler is to remain disabled.):
• The horizontal and vertical size of the source image
• The horizontal and vertical scaling factors to be used to
scale the source image
• The filter coefficients
The timing registers (DC Memory Offsets 040h-058h)
should be programmed based on the parameters for the
resulting output image. Note that this image may differ in
size from the frame buffer image. The frame buffer image
size is used to determine the value to be written to the
Frame Buffer Active Region Register (DC Memory Offset
05Ch).
The scaling factors are programmed into the Graphics Fil-
ter Scale Register (DC Memory Offset 090h). These fields
are 16 bits each (horizontal and vertical). The 16 bits repre-
sent the ratio of the destination image size to the source
image size. They are right-shifted 14 bits to represent frac-
tional values between 0 and 3.99993896484375. However,
due to hardware limitations, the downscale factors cannot
exceed 2.0. Thus the image can be downscaled by nearly
2X in the horizontal and vertical directions. The image can
be upscaled by up to 16384X, although the CRTC does not
support images beyond 1920x1440 pixels, so it is unlikely
that scale factors beyond about 4X would ever be used.
VBI data is not filtered. The scaling factors in the Graphics
Filter Scale register have no effect on VBI data.
The filter supports 256 sub-pixel phases in both the hori-
zontal and vertical directions. Each coefficient is 10 bits,
and is represented as a 2’s compliment number, right-
shifted 9 bits to represent values between -1 and
0.998046875. The coefficients must be loaded into the
RAMs by software, using the IRQ/Filter Control register, Fil-
ter Coefficient Data register 1, and Filter Coefficient Data
Register 2 (DC Memory Offsets 094h-09Ch).