Filter
Top Products
AMD Geode™ LX Processors Data Book 417
Video Processor Register Descriptions
33234H
6.8.1.3 GLD SMI MSR (GLD_MSR_SMI)
The Video Processor does not produce SMI interrupts, therefore this register is not used. Always write 0.
6.8.1.4 GLD Error MSR (GLD_MSR_ERROR)
MSR Address 48002002h
Typ e R /W
Reset Value 00000000_00000000h
MSR Address 48002003h
Typ e R /W
Reset Value 00000000_00000000h
GLD_MSR_ERROR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RSVD
E
313029282726252423222120191817161514131211109876543210
RSVD
EM
GLD_MSR_ERROR Bit Descriptions
Bit Name Description
63:33 RSVD (RO) Reserved (Read Only). Reads back as 0.
32 E VP Error Status. Any GLIU request made of an unsupported function type causes this
bit to be set by the hardware. Writing a 1 to this bit clears the status. Bit 0 must be 0 for
the error to be generated.
0: Error not pending.
1: Error pending.
31:1 RSVD (RO) Reserved (Read Only).
0EM DF Error Mask.
0: Unmask the Error (i.e., error generation is enabled).
1: Mask the Error (i.e., error generation is disabled).