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AMD Geode™ LX Processors Data Book 135
CPU Core Register Descriptions
33234H
5.5.2.27 Debug Registers 1 and 0 MSR (DR1_DR0_MSR)
DR1_DR0_MSR provides access to Debug Register 1 (DR1) and Debug Register 0 (DR0). DR0 and DR1 each contain
either an I/O port number or a linear address for use as a breakpoint. The contents of debug registers are more easily
accessed using the MOV instruction.
5.5.2.28 Debug Registers 3 and 2 MSR (DR3_DR2_MSR)
DR3/DR2_MSR provides access to Debug Register 3 (DR3) and Debug Register 2 (DR2). DR2 and DR3 each contain
either an I/O port number or a linear address for use as a breakpoint. The contents of debug registers are more easily
accessed using the MOV instruction.
MSR Address 00001340h
Typ e R /W
Reset Value xxxxxxxx_xxxxxxxxh
DR1_DR0_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
DR1
313029282726252423222120191817161514131211109876543210
DR0
DR1_DR0_MSR Bit Descriptions
Bit Name Description
63:32 DR1 Breakpoint 1 I/O Port Number/Linear Address.
31:0 DR0 Breakpoint 0 I/O Port Number/Linear Address.
MSR Address 00001341h
Typ e R /W
Reset Value xxxxxxxx_xxxxxxxxh
DR3_DR2_MSR Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
DR3
313029282726252423222120191817161514131211109876543210
DR2
DR2_DR3_MSR Bit Descriptions
Bit Name Description
63:32 DR3 Breakpoint 3 I/O Port Number/Linear Address.
31:0 DR2 Breakpoint 2 I/O Port Number/Linear Address.