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8.4.15InterruptPriorityRegister4(INTPRI4)
8.4.16InterruptPriorityRegister5(INTPRI5)
AINTCRegisters
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Theinterruptpriorityregister4(INTPRI4)isshowninFigure8-19anddescribedinTable8-17.
Figure8-19.InterruptPriorityRegister4(INTPRI4)
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ReservedINT39ReservedINT38ReservedINT37ReservedINT36
R-0R/W-7hR-0R/W-7hR-0R/W-7hR-0R/W-7h
15141211108764320
ReservedINT35ReservedINT34ReservedINT33ReservedINT32
R-0R/W-7hR-0R/W-7hR-0R/W-7hR-0R/W-7h
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table8-17.InterruptPriorityRegister4(INTPRI4)FieldDescriptions
BitFieldValueDescription
Reserved0Reserved
INTn0-7hSelectsINTnprioritylevel.
Theinterruptpriorityregister5(INTPRI5)isshowninFigure8-20anddescribedinTable8-18.
Figure8-20.InterruptPriorityRegister5(INTPRI5)
313028272624232220191816
ReservedINT47ReservedINT46ReservedINT45ReservedINT44
R-0R/W-7hR-0R/W-7hR-0R/W-7hR-0R/W-7h
15141211108764320
ReservedINT43ReservedINT42ReservedINT41ReservedINT40
R-0R/W-7hR-0R/W-7hR-0R/W-7hR-0R/W-7h
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table8-18.InterruptPriorityRegister5(INTPRI5)FieldDescriptions
BitFieldValueDescription
Reserved0Reserved
INTn0-7hSelectsINTnprioritylevel.
ARMInterruptController(AINTC) 100SPRUEP9A–May2008
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