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5.4.14ClockStatusRegister(CKSTAT)
PLLControllerRegisterMap
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Theclockstatusregister(CKSTAT)isshowninFigure5-17anddescribedinTable5-18.Clockstatusfor
allclocks,exceptSYSCLKn.CKSTATisnotusedonPLL2.
Figure5-17.ClockStatusRegister(CKSTAT)
3116
Reserved
R-0
1543210
ReservedBPONReservedAUXEN
R-0R-1R-0R-0
LEGEND:R=Readonly;-n=valueafterreset
Table5-18.ClockStatusRegister(CKSTAT)FieldDescriptions
BitFieldValueDescription
31-4Reserved0Reserved
3BPONSYSCLKBPonstatus.
0Off
1On
2-1Reserved0Reserved
0AUXENAUXCLKonstatus.
0Off
1On
PLLController 58SPRUEP9A–May2008
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