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3.4ExceptionsandExceptionVectors
ExceptionsandExceptionVectors
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Exceptionsarisewhenthenormalflowoftheprogrammustbetemporarilyhalted.Theexceptionsthat
occurinanARMsystemaregivenbelow:
•Resetexception:processorreset
•FIQinterrupt:fastinterrupt
•IRQinterrupt:normalinterrupt
•Abortexception:abortindicatesthatthecurrentmemoryaccesscouldnotbecompleted.Theabort
couldbeapre-fetchabortoradataabort.
•SWIinterrupt:usesoftwareinterrupttoentersupervisormode.
•Undefinedexception:occurswhentheprocessorexecutesanundefinedinstruction
Theexceptionsintheorderofhighestprioritytolowestpriorityare:reset,dataabort,FIQ,IRQ,pre-fetch
abort,undefinedinstruction,andSWI.SWIandundefinedinstructionhavethesamepriority.Depending
uponthestatusofVINTHsignalortheregistersettinginCP15,thevectortablecanbelocatedataddress
00000000h(VINTH=0)orataddressFFFF0000h(VINTH=1).
Note:ThisisafeatureofthestandardARM9code.However,thereisnomemoryintheDMSoCin
thisaddressregion,sodonotsetthisbit.
ThedefaultvectortableisshowninTable3-1
Table3-1.ExceptionVectorTableforARM
VectorOffsetAddressExceptionModeonentryIBitStateonEntryFBitStateonEntry
0hResetSupervisorSetSet
4hUndefinedinstructionUndefinedSetUnchanged
8hSoftwareinterruptSupervisorSetUnchanged
ChPre-fetchabortAbortSetUnchanged
10hDataabortAbortSetUnchanged
14hReserved---
18hIRQIRQSetUnchanged
1ChFIQFIQSetSet
ARMCore 22SPRUEP9A–May2008
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