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4.2.2.1AsynchronousEMIF(EMIFA)
4.2.2.2NAND(NAND,SmartMedia,xD)
4.2.2.3ATAController
MemoryInterfacesOverview
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TheasynchronousEMIF(EMIFA)providesboththeEMIFAandNANDinterfaces.Fourchipselectsare
provided.EachisindividuallyconfigurabletoprovideeitherEMIFAorNANDsupport.
•TheEMIFAmodesupportsasynchronousdevices(RAM,ROM,andNORFlash)
•128MBasynchronousaddressrangeover4chipselects(32MBeach)
•Supports8-bitor16-bitdatabuswidths
•Programmableasynchronouscycletimings
•Supportsextendedwaits
•SupportsSelectStrobemode
•SupportsTIDSPHPIinterface
•SupportsbootingDM646xDMSoCARMprocessorfromCS2(SRAM/NORFlash)
TheasynchronousEMIF(EMIFA)providesboththeEMIFAandNANDinterfaces.Fourchipselectsare
providedandeachisindividuallyconfigurabletoprovideeitherEMIFAorNANDsupport.
•TheNANDModesupportsNANDFlashonupto4asynchronouschipselects
•Supports8-bitdatabuswidth
•Programmablecycletimings
•PerformsECCcalculation
•NANDModealsosupportsSmartMedia/SSFDC(SolidStateFloppyDiskController)andxDmemory
cards
•ARMROMsupportsbootingoftheDM646xDMSoCARMprocessorfromNAND-FlashlocatedatCS2
TheATAcontrollerprovidesthefollowingcapabilities:
•SupportsPIO,multi-wordDMA,andUltraATA33/44/66/100
•Supportsuptomode4timingsonPIOmode
•Supportsuptomode2timingsonmulti-wordDMA
•Supportsuptomode5timingsonUltraATA
•FullscattergatherDMAcapability
•SinglechannelcapableofconnectinguptotwoATA/ATAPIdevices
•ProgrammabletimingfeaturesenabletimingparameterstobereprogrammedtosupportanyATA
timingmodeatanyclockfrequency
Additionally,theHostIDEControllersupportsmulti-wordDMAandUltraDMAdatatransfersbetween
externalIDE/ATAPIdevicesandasystemmemorybusinterface.Thetimingandcontrolregistersinthis
corearecompatibletotheIntelregistersetinthePIIXfamily.
ThiscorehasafullscattergatherDMAcapability,whichiscompatiblewiththeIntelscattergatherDMA
functiononthePIIXchipset.
32SystemMemorySPRUEP9A–May2008
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