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5.4.7PLLControllerDivider3Register(PLLDIV3)
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PLLControllerRegisterMap
ThePLLcontrollerdivider3register(PLLDIV3)isshowninFigure5-10anddescribedinTable5-11.
Divider3controlsthedividerforSYSCLK3.PLLDIV3isnotusedonPLL2.
Note:OntheDM646xDMSoC,allPLL1SYSCLKndividersareprogrammablebutyoushouldnot
changethedividervaluetomaintaintheclockratiosbetweenvariousmodulesofthedevice.
Youshouldonlyusethepower-updefaultdividervaluesforallPLL1SYSCLKndividersfor
normaldeviceoperation.
Figure5-10.PLLControllerDivider3Register(PLLDIV3)
3116
Reserved
R-0
1514430
D3ENReservedRATIO
R/W-1R-0R/W-3h
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table5-11.PLLControllerDivider3Register(PLLDIV3)FieldDescriptions
BitFieldValueDescription
31-16Reserved0Reserved
15D3ENDividerenableforSYSCLK3.
0Disable
1Enable
14-4Reserved0Reserved
3-0RATIO0-FhDividerratio.DividerValue=RATIO+1.RATIOdefaultsto3h(PLLdivideby4).
SPRUEP9A–May2008PLLController51
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