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5.4.16PLLControllerDividernRegisters(PLLDIV4-PLLDIV6,PLLDIV8,PLLDIV9)
PLLControllerRegisterMap
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ThePLLcontrollerdividernregister(PLLDIVn)isshowninFigure5-19anddescribedinTable5-20.
PLLDIV4controlsthedividerforSYSCLK4,PLLDIV5controlsthedividerforSYSCLK5,PLLDIV6controls
thedividerforSYSCLK6,PLLDIV8controlsthedividerforSYSCLK8,andPLLDIV9controlsthedividerfor
SYSCLK9.PLLDIVnisnotusedonPLL2.
Note:OntheDM646xDMSoC,allPLL1SYSCLKndividersareprogrammablebutyoushouldnot
changethedividervaluetomaintaintheclockratiosbetweenvariousmodulesofthedevice.
Youshouldonlyusethepower-updefaultdividervaluesforallPLL1SYSCLKndividersfor
normaldeviceoperation.
Figure5-19.PLLControllerDividernRegister(PLLDIVn)
3116
Reserved
R-0
1514430
DnENReservedRATIO
R/W-1R-0R/W-5hor7h
(1)
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
(1)
ForPLLDIV4andPLLDIV9,RATIOdefaultsto5(PLLdivideby6);forPLLDIV5,PLLDIV6,andPLLDIV8,RATIOdefaultsto7(PLL
divideby8).
Table5-20.PLLControllerDividernRegister(PLLDIVn)FieldDescriptions
BitFieldValueDescription
31-16Reserved0Reserved
15DnENDividerenableforSYSCLKn.
0Disable
1Enable
14-4Reserved0Reserved
3-0RATIO0-FhDividerratio.DividerValue=RATIO+1.
60PLLControllerSPRUEP9A–May2008
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