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5.1PLLModule
PLLModule
www.ti.com
TheTMS320DM646xDMSoChastwoPLLcontrollersthatprovideclockstodifferentpartsofthesystem
(seeFigure5-1).PLL1providesclocks(thoughvariousdividers)tomostofthecomponentsofthe
DMSoC.PLL2isdedicatedtotheDDR2memorycontroller.Therecommendedreferenceclockisa
27-MHZcrystalinput.Seethedevice-specificdatamanualforthesupportedinputclocks.
ThePLLcontrollerprovidesthefollowing:
•Glitch-FreeTransitions(onchangingclocksettings)
•DomainClocksAlignment
•ClockGating
•PLLpowerdown
Thevariousclockoutputsgivenbythecontrollerare:
•DomainClocks:SYSCLK[1:n]
•AuxiliaryClockfromreferenceclocksource:AUXCLK
•BypassDomainclock:SYSCLKBP
Variousdividersthatcanbeusedare:
•SYSCLKDivider:D1,…,Dn
•SYSCLKBPDivider:BPDIV
Variousothercontrolssupportedare:
•PLLMultiplierControl:PLLM
•SoftwareprogrammablePLLBypass:PLLEN
PLLController 36SPRUEP9A–May2008
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