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5.4PLLControllerRegisterMap
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PLLControllerRegisterMap
Table5-3.PLLandResetControllerModuleInstanceTable
InstanceIDBaseAddressEndAddressSize
01C40800h1C40BFFh400h
11C40C00h1C40FFFh400h
Table5-4liststhememory-mappedregistersforthePLLandResetController.Seethedevice-specific
datamanualforthememoryaddressoftheseregisters.
Table5-4.PLLandResetControllerRegisters
OffsetAcronymRegisterDescriptionSection
00hPIDPeripheralIDRegisterSection5.4.1
E4hRSTYPEResetTypeStatusRegisterSection5.4.2
100hPLLCTLPLLControlRegisterSection5.4.3
110hPLLMPLLMultiplierControlRegisterSection5.4.4
118hPLLDIV1PLLControllerDivider1RegisterSection5.4.5
11ChPLLDIV2
(1)
PLLControllerDivider2RegisterSection5.4.6
120hPLLDIV3
(1)
PLLControllerDivider3RegisterSection5.4.7
12ChBPDIV
(1)
BypassDividerRegisterSection5.4.8
138hPLLCMDPLLControllerCommandRegisterSection5.4.9
13ChPLLSTATPLLControllerStatusRegisterSection5.4.10
140hALNCTLPLLControllerClockAlignControlRegisterSection5.4.11
144hDCHANGEPLLDIVRatioChangeStatusRegisterSection5.4.12
148hCKENClockEnableControlRegisterSection5.4.13
14ChCKSTATClockStatusRegisterSection5.4.14
150hSYSTATSYSCLKStatusRegisterSection5.4.15
160hPLLDIV4
(1)
PLLControllerDivider4RegisterSection5.4.16
164hPLLDIV5
(1)
PLLControllerDivider5RegisterSection5.4.16
168hPLLDIV6
(1)
PLLControllerDivider6RegisterSection5.4.16
170hPLLDIV8
(1)
PLLControllerDivider8RegisterSection5.4.16
174hPLLDIV9
(1)
PLLControllerDivider9RegisterSection5.4.16
(1)
ForPLL1only,notsupportedforPLL2
SPRUEP9A–May2008PLLController45
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