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efficiency.TheinternalmemoryarchitectureintheC621x/C671x/C64xDSPsisorganizedina
two-levelhierarchyconsistingofadedicatedprogramcache(L1P)andadedicateddatacache
(L1D)onthefirstlevel.AccessesbytheCPUtothethesefirstlevelcachescancompletewithout
CPUpipelinestalls.IfthedatarequestedbytheCPUisnotcontainedincache,itisfetchedfrom
thenextlowermemorylevel,L2orexternalmemory.
SPRU862—TMS320C64x+DSPCacheUser'sGuide.Explainsthefundamentalsofmemorycaches
anddescribeshowthetwo-levelcache-basedinternalmemoryarchitectureintheTMS320C64x+
digitalsignalprocessor(DSP)oftheTMS320C6000DSPfamilycanbeefficientlyusedinDSP
applications.Showshowtomaintaincoherencewithexternalmemory,howtouseDMAtoreduce
memorylatencies,andhowtooptimizeyourcodetoimprovecacheefficiency.Theinternalmemory
architectureintheC64x+DSPisorganizedinatwo-levelhierarchyconsistingofadedicated
programcache(L1P)andadedicateddatacache(L1D)onthefirstlevel.AccessesbytheCPUto
thethesefirstlevelcachescancompletewithoutCPUpipelinestalls.Ifthedatarequestedbythe
CPUisnotcontainedincache,itisfetchedfromthenextlowermemorylevel,L2orexternal
memory.
ReadThisFirst 12SPRUEP9A–May2008
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