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5.3.2.1.2PLL2FrequencyChangeStepsWhenDDR2MemoryControllerisOutofReset
5.3.2.2InitializationtoPLLModefromPLLPowerDown
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PLL2Control
ThissectiondiscussesthestepstochangethePLL2frequencywhentheDDR2memorycontrolleris
alreadyoutofreset.
1.StopDDR2memorycontrolleraccessesandpurgeanyoutstandingrequests.
2.PuttheDDR2memoryinself-refreshmodeandstoptheDDR2memorycontrollerclock.TheDDR2
memorycontrollerclockshutdownsequenceisintheTMS320DM646xDMSoCDDR2Memory
ControllerUser'sGuide(SPRUEQ4).
3.ProgramthePLL2clocksbyfollowingthestepsintheappropriatesection:Section5.3.2.2,
Section5.3.2.3,orSection5.3.2.4.(DiscussioninSection5.3.2explainswhichistheappropriate
subsection).
4.Re-enabletheDDR2memorycontrollerclock.TheDDR2memorycontrollerclockonsequenceisin
theTMS320DM646xDMSoCDDR2MemoryControllerUser'sGuide(SPRUEQ4).
IfthePLLispowereddown(PLLPWRDNbitinPLLCTLissetto1),followthisproceduretochangePLL2
frequencies.
1.SelecttheclockmodebyprogrammingtheCLKMODEbitinPLLCTL.
2.BeforechangingthePLLfrequency,switchtoPLLbypassmode:
a.ClearthePLLENSRCbitinPLLCTLto0toallowPLLCTL.PLLENtotakeeffect.
b.ClearthePLLENbitinPLLCTLto0(selectPLLbypassmode).
c.Waitfor20MXIclockcyclestoensurePLLCswitchestobypassmodeproperly.
3.SetthePLLRSTbitinPLLCTLto1(resetPLL)
4.SetthePLLDISbitinPLLCTLto1(disablePLLoutput).
5.ClearthePLLPWRDNbitinPLLCTLto0tobringthePLLoutofpower-downmode.
6.ClearthePLLDISbitinPLLCTLto0(enablethePLL)toallowPLLoutputstostarttoggling.Notethat
thePLLCisstillatPLLbypassmode;therefore,thetogglingPLLoutputdoesnotgetpropagatedto
therestofthedevice.
7.WaitforPLLstabilizationtime.(4096MXIclockcycles)
8.ProgramtherequiredmultipliervalueinthePLLmultipliercontrolregister(PLLM).
9.Ifnecessary,programthePLLcontrollerdivider1register(PLLDIV1)tochangetheSYSCLK1divide
value:
a.ProgramtheRATIOfieldinPLLDIV1withthedesireddividefactor.
b.SettheGOSETbitinPLLCMDto1toinitiateanewdividertransition.
c.WaitfortheGOSTATbitinthePLLcontrollerstatusregister(PLLSTAT)toclearto0(completionof
phasealignment).
10.WaitforPLLtoresetproperly.ThePLLresettimeisaminimumof32MXIclockcycles.
11.ClearthePLLRSTbitinPLLCTLto0tobringthePLLoutofreset.
12.Waitfor2000MXIclockorreferenceclockcyclestoallowPLLtolock.
13.SetthePLLENbitinPLLCTLto1toremovethePLLfrombypassmode.
ForinformationoninitializingtheDDR2memorycontroller,seetheTMS320DM646xDMSoCDDR2
MemoryControllerUser'sGuide(SPRUEQ4).
SPRUEP9A–May2008PLLController43
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