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3.2OperatingStates/Modes
3.3ProcessorStatusRegisters
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OperatingStates/Modes
TheARMcanoperateintwostates:ARM(32-bit)modeandThumb(16-bit)mode.Youcanswitchthe
ARM926EJ-SprocessorbetweenARMmodeandThumbmodeusingtheBXinstruction.
TheARMcanoperateinthefollowingmodes:
•Usermode(USR):Non-privilegedmode,usuallyfortheexecutionofmostapplicationprograms.
•Fastinterruptmode(FIQ):Fastinterruptprocessing
•Interruptmode(IRQ):Normalinterruptprocessing
•Supervisormode(SVC):Protectedmodeofexecutionforoperatingsystems
•Abortmode(ABT):Modeofexecutionafteradataabortorapre-fetchabort
•Systemmode(SYS):Privilegedmodeofexecutionforoperatingsystems
•Undefinedmode(UND):ExecutinganundefinedinstructioncausestheARMtoenterundefinedmode.
Youcanonlyenterprivilegedmodes(systemorsupervisor)fromotherprivilegedmodes.
Toentersupervisormodefromusermode,generateasoftwareinterrupt(SWI).AnIRQinterruptcauses
theprocessortoentertheIRQmode.AnFIQinterruptcausestheprocessortoentertheFIQmode.
Differentstacksmustbesetupfordifferentmodes.Thestackpointer(SP)automaticallychangestothe
SPofthemodethatwasentered.
Theprocessorstatusregister(PSR)controlstheenablinganddisablingofinterruptsandsettingthemode
ofoperationoftheprocessor.The8least-significantbits,PSR[7:0],arethecontrolbitsoftheprocessor.
PSR[27:8]arereservedbitsandPSR[31:28]arestatusbits.Thedetailsofthecontrolbitsare:
•Bit7-Ibit:DisableIRQ(I=1)orenableIRQ(I=0)
•Bit6-Fbit:DisableFIQ(F=1)orenableFIQ(F=0)
•Bit5-Tbit:Controlswhethertheprocessorisinthumbmode(T=1)orARMmode(T=0)
•Bits4:0Mode:Controlsthemodeofoperationoftheprocessor
–PSR[4:0]=10000:Usermode
–PSR[4:0]=10001:FIQmode
–PSR[4:0]=10010:IRQmode
–PSR[4:0]=10011:Supervisormode
–PSR[4:0]=10111:Abortmode
–PSR[4:0]=11011:Undefinedmode
–PSR[4:0]=11111:Systemmode
StatusbitsshowtheresultofthemostrecentALUoperation.Thedetailsofthestatusbitsare:
•Bit31-Nbit:Negativeorlessthan
•Bit30-Zbit:Zero
•Bit29-Cbit:Carryorborrow
•Bit28-Vbit:Overfloworunderflow
Note:SeeChapter2oftheProgrammer’sModeloftheARM926EJ-STRM,downloadablefrom
http://www.arm.com/arm/TRMsformoredetailedinformation.
SPRUEP9A–May2008ARMCore21
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