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5.4.13ClockEnableControlRegister(CKEN)
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PLLControllerRegisterMap
Theclockenablecontrolregister(CKEN)isshowninFigure5-16anddescribedinTable5-17.Clock
enablecontrolformiscellaneousoutputclocks.CKENisnotusedonPLL2.
Figure5-16.ClockEnableControlRegister(CKEN)
3116
Reserved
R-0
1510
ReservedAUXEN
R-0R/W-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table5-17.ClockEnableControlRegister(CKEN)FieldDescriptions
BitFieldValueDescription
31-1Reserved0Reserved
0AUXENAUXCLKenable.Theactualclockstatusisshownintheclockstatusregister(CKSTAT).
0Clockisdisabled.
1Clockisenabled.
SPRUEP9A–May2008PLLController57
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