Texas Instruments TMS320DM646x Computer Hardware User Manual


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5.3PLL2Control
PLLDIV1(/1Prog)
PLL2_SYSCLK1
(DDR2_PHY)
1
0
PLLEN
PLL
PLLM
CLKIN/OSCIN
(A)
(A) AsselectedbythePLL2PLLCTL register
PLLOUT
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PLL2Control
PLL2providestheclockfromwhichtheDDR2memorycontrollerclockisderived.Thisisaseparateclock
systemfromthePLL1clocksprovidedtoothercomponentsofthesystem.Thisdedicatedclockallowsthe
reductionofthecoreclockratestosavepowerwhilemaintainingtherequiredminimumclockratefor
DDR2.PLL2mustbeconfiguredtooutputa2xclocktotheDDR2PHYinterface.
TheDDR2PLLcontroller(PLLC2)controlsPLL2,whichacceptstheclockfromtheoscillatorand
generatesthevariousfrequencyclocksneededfortheDDR2memorycontroller.Figure5-3showsthe
customizationofPLL2intheDM646xDMSoC.
•TheSYSCLKdividerisprogrammable.
•AUXCLKandSYSCLKBParenotused.
PLL2suppliestheDDR2memorycontrollerclock.SoftwarecontrolsPLL2operationthroughthePLLC2
registers.ThePLLMbitsinthePLLmultipliercontrolregister(PLLM)controlthePLL2multiplier.The
PLL2multipliermaybemodifiedbysoftware(forexample,totunetheDDR2memorycontrollerinterface
forbestperformance).
ThePLL2outputclockmustbedivided-downtotheDDR2memorycontrolleroperatingrange.
Atpower-up,PLL2ispowered-downandmustbepowered-upbysoftwarethroughthePLLPWRDNbitin
thePLLcontrolregister(PLLCTL).ThePLLC2isinbypassmodeandtheDDR2memorycontrollerclock
isprovideddirectlyfromtheinputreferenceclock.OncethePLLispowered-upandlocked,softwaremay
switchthedevicetoPLLmodeoperationbysettingthePLLENbitinPLLCTL.
RegistersusedinPLLC2arelistedinTable5-4.
Note:PLLDIV1defaultsto/1atresetandcanbemodifiedafterreset.PLLDIV2throughPLLDIV9
arenotsupportedonPLL2.
Figure5-3.PLL2StructureinTMS320DM646xDMSoC
SPRUEP9A–May2008PLLController41
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