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9.6.8ARMMemoryWaitStateControl
9.7BandwidthManagement
9.7.1BusMasterDMAPriorityControl
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BandwidthManagement
TheARMmemorywaitstatecontrolregister(ARMWAIT)isusedtocontrolARM926accessestoitsTCM
RAM.AtnormalARMoperatingfrequency,awaitstatemustbeinsertedwhenaccessingTCMRAM.
Whenthedeviceisoperatingatlowerspeeds,performancemaybeincreasedbyremovingthewaitstate.
NotethattheTCMROMwillalwaysoperatewithawaitstateenabled.Seethedevice-specificdata
manualfordetailsonARMWAIT.
Inordertodetermineallowedconnectionsbetweenmastersandslaves,eachmasterrequestsourcemust
haveauniquemasterID(mstid)associatedwithit.ThemasterIDforeachDM646xDMSoCmasteris
showninTable9-1.
Table9-1.TMS320DM646xDMSoCMasterIDs
mstidMaster
0ARMInstruction
1ARMData
2DSPMDMA
3DSPCFG
4-7Reserved
8HDVICP0CFG
9HDVICP1CFG
10EDMA3CCTR
11-15Reserved
16EDMA3TC0read
17EDMA3TC0write
18EDMA3TC1read
19EDMA3TC1write
20EDMA3TC2read
21EDMA3TC2write
22EDMA3TC3read
23EDMA3TC3write
24-31Reserved
32PCI
33HPI
34ATA
35EMAC
36USB
37VLYNQ
38VPIFmstr1read
39VPIFmstr0write
40TSIF0read
41TSIF0write
42TSIF1read
43TSIF1write
44VDCEwrite
45VDCEread
46-63Reserved
SPRUEP9A–May2008SystemControlModule107
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