Texas Instruments TMS320DM646x Computer Hardware User Manual


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5.2PLL1Control
PLLDIV1(/1Prog)
PLLDIV2(/2Prog)
PLLDIV3(/4Prog)
PLLDIV4(/6Prog)
PLLDIV5(/8Prog)
PLLDIV6(/8Prog)
PLLDIV8(/8Prog)
PLLDIV9(/6Prog)
BPDIV(/1Prog)
SYSCLK1
SYSCLK2
SYSCLK3
SYSCLK4
SYSCLK5
SYSCLK6
SYSCLK8
SYSCLK9
SYSCLKBP
AUXCLK
1
0
PLLEN
PLL
1
0
CLKMODE
PLLM
CLKIN
OSCIN
PLLOUT
PLL1Control
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PLL1suppliestheprimaryDM646xDMSoCsystemclock.SoftwarecontrolsthePLL1operationthrough
thesystemPLLcontroller1(PLLC1)registers(baseaddress:1C40800h).Figure5-2showsthe
customizationofPLL1intheDM646xDMSoC.
•TheSYSCLKdividersareprogrammable(seeTable5-1).
•AUXCLKistheclockprovidedtothefixedclockdomains
ThePLL1multiplieriscontrolledbythePLLMbitinthePLLmultipliercontrolregister(PLLM)andissetto
adefaultvalueof15hatpower-up,resultinginaPLLmultiplierof22×.Thisdefaultsettingyieldsa
594-MHZPLLoutputclockwhenusinga27-MHZclocksource.ThePLL1multipliermaybemodifiedby
software(forexample,setto18×fora486-MHZoperation).
Atpower-up,PLL1ispowered-down/disabledandmustbepowered-upbysoftwarethroughthe
PLLPWRDNbitinthePLLcontrolregister(PLLCTL).Thesystemoperatesinbypassmodeandthe
systemclockisprovideddirectlyfromtheinputreferenceclock(CLKINorOSCIN).OncethePLLis
powered-upandlocked,softwarecanswitchthedevicetoPLLmodeoperation.SetthePLLENbitin
PLLCTLtoenablethePLL.
RegistersusedinPLLC1arelistedinTable5-4
Figure5-2.PLL1StructureintheTMS320DM646xDMSoC
PLLController 38SPRUEP9A–May2008
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