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InterruptMapping
Table8-1.ARMInterruptMap
ARMARM
InterruptInterrupt
NumberAcronymSourceNumberAcronymSource
0VP_VERTINT0VPIF32TINTL0Timer0lower–TINT12
1VP_VERTINT1VPIF33TINTH0Timer0upper–TINT34
2VP_VERTINT2VPIF34TINTL1Timer1lower–TINT12
3VP_VERTINT3VPIF35TINTH1Timer1upper–TINT34
4VP_ERRINTVPIF36PWMINT0PWM0
5-Reserved37PWMINT1PWM1
6-Reserved38VLQINTVLYNQ
7WDINTWDTimer(TIMER2)–39I2CINTI2C
TINT12
8CRGENINT0CRGEN040UARTINT0UART0
9CRGENINT1CRGEN141UARTINT1UART1
10TSINT0TSIF042UARTINT2UART2
11TSINT1TSIF143SPINT0SPI
12VDCEINTVDCE44SPINT1SPI
13USBINTUSB45DSP2ARM0DSPControllertoARM
14USBDMAINTUSBDMA46-Reserved
15PCIINTPCI47PSCINTPowerandSleep
Controller
16CCINT0EDMACCRegion048GPIO0GPIO
17CCERRINTEDMACCError49GPIO1GPIO
18TCERRINT0EDMATC0Error50GPIO2GPIO
19TCERRINT1EDMATC1Error51GPIO3GPIO
20TCERRINT2EDMATC2Error52GPIO4GPIO
21TCERRINT3EDMATC3Error53GPIO5GPIO
22IDEINTATA54GPIO6GPIO
23HPIINTHPI55GPIO7GPIO
24MAC_RXTHEMACReceive56GPIOBNK0GPIOBank0
Threshold
25MAC_RXEMACReceive57GPIOBNK1GPIOBank1
26MAC_TXEMACTransmit58GPIOBNK2GPIOBank2
27MAC_MISCEMACMiscellaneous59DDRINTDDR2MemoryController
28AXINT0McASP0Transmit60EMIFAINTEMIFA
29ARINT0McASP0Receive61COMMTXARMSS
30AXINT1McASP1Transmit62COMMRXARMSS
31-Reserved63EMUINTE2ICE
SPRUEP9A–May2008ARMInterruptController(AINTC)87
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