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7.4.2DSPSleepModes.................................................................................................82
7.5I/OManagement............................................................................................................83
7.5.13.3VI/OPower-Down............................................................................................83
7.6USBPhyPowerDown.....................................................................................................83
8ARMInterruptController(AINTC)...............................................................................85
8.1Introduction..................................................................................................................86
8.2InterruptMapping...........................................................................................................86
8.3AINTCMethodology.......................................................................................................88
8.3.1InterruptMapping..................................................................................................88
8.3.2InterruptPrioritization.............................................................................................89
8.3.3VectorTableEntryAddressGeneration.......................................................................89
8.3.4ClearingInterrupts.................................................................................................90
8.3.5EnablingandDisablingInterrupts...............................................................................90
8.4AINTCRegisters...........................................................................................................91
8.4.1FastInterruptRequestStatusRegister0(FIQ0)..............................................................92
8.4.2FastInterruptRequestStatusRegister1(FIQ1)..............................................................92
8.4.3InterruptRequestStatusRegister0(IRQ0)...................................................................93
8.4.4InterruptRequestStatusRegister1(IRQ1)...................................................................93
8.4.5FastInterruptRequestEntryAddressRegister(FIQENTRY)...............................................94
8.4.6InterruptRequestEntryAddressRegister(IRQENTRY).....................................................94
8.4.7InterruptEnableRegister0(EINT0)............................................................................95
8.4.8InterruptEnableRegister1(EINT1)............................................................................95
8.4.9InterruptOperationControlRegister(INTCTL)................................................................96
8.4.10InterruptEntryTableBaseAddressRegister(EABASE)...................................................97
8.4.11InterruptPriorityRegister0(INTPRI0)........................................................................98
8.4.12InterruptPriorityRegister1(INTPRI1)........................................................................98
8.4.13InterruptPriorityRegister2(INTPRI2)........................................................................99
8.4.14InterruptPriorityRegister3(INTPRI3)........................................................................99
8.4.15InterruptPriorityRegister4(INTPRI4).......................................................................100
8.4.16InterruptPriorityRegister5(INTPRI5).......................................................................100
8.4.17InterruptPriorityRegister6(INTPRI6).......................................................................101
8.4.18InterruptPriorityRegister7(INTPRI7).......................................................................101
9SystemControlModule...........................................................................................103
9.1OverviewoftheSystemControlModule..............................................................................104
9.2DeviceIdentification......................................................................................................104
9.3DeviceConfiguration.....................................................................................................105
9.3.1PinMultiplexingControl........................................................................................105
9.3.2DeviceBootConfigurationStatus.............................................................................105
9.3.3DeviceBootProcessStatus....................................................................................105
9.4ARM-DSPIntegration....................................................................................................105
9.4.1ARM-DSPInterruptControlandStatus.......................................................................105
9.4.2DSPBootAddressControlandStatus.......................................................................105
9.5PowerManagement......................................................................................................106
9.5.1V
DD
3.3VI/OPower-DownControl............................................................................106
9.6SpecialPeripheralStatusandControl.................................................................................106
9.6.1UniversalSerialBus(USB)InterfaceControl................................................................106
9.6.2HostPortInterface(HPI)Control..............................................................................106
9.6.3VideoClockControlandDisable..............................................................................106
SPRUEP9A–May2008Contents5
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